In many electronic devices that provide for digital to analog conversion, an input analog signal is sampled, amplified and converted into a digital data signal in an analog front end (AFE) circuit so as to convert the input analog signal into the digital data signal. The AFE circuit typically employs a programmable gain amplifier (PGA) that adjusts a gain characteristic appropriate for input analog signals having various amplitudes.
The PGA typically controls the gain using a capacitor array rather than a resistor array because the PGA is implemented by an integrated circuit. In particular, the PGA switches an input signal in response to first and second clock signals to output an amplified signal.
A switched capacitor circuit receives an input clock signal and first and second clock signals. The active (or inactive) period of the first and second clock signals typically do not overlap each other. The first clock signal typically has an inverted phase with respect to the second clock signal.
The first clock signal may have the same phase as that of the input clock signal, and the second clock signal have an inverted phase with respect to the input clock signal. Typically, to provide the different phases of the first and second clock signals, the first clock signal passes through an even number of inverters, and the second clock signal passes through an odd number of inverters. Thus, there is a difference between the number of the inverters through which the first clock signal passes and the number of the inverters through which the second clock signal passes. The difference is typically an odd number of inverters, or at least one. When the difference is one, the first clock signal has a timing skew corresponding to one inverter with respect to the second clock signal. The timing skew may cause problems when the PGA is implemented for high speed applications.
Thus, conventionally, a signal path of the first clock signal and a signal path of the second clock cross each other so as to reduce the timing skew corresponding to one inverter. The timing skew corresponding to a delay of one inverter is divided between (or shared by) the first and second clock signals, and thus the first clock signal has a same timing skew characteristic as that of the second clock signal.
However, according to above method, the duty ratio of the first clock signal having the same phase as that of the input clock signal is less than that of the second clock signal having the inverted phase with respect to the input clock signal due to the difference of the numbers of inverters through which the first and second clock signals pass. The duty ratio difference between the first and second clock signals may lower the reliability of the operation of the PGA.